1. Field of the Invention
The present invention relates to a pattern data correction method, a pattern checking method, a pattern check program, a photo mask producing method, and a semiconductor device manufacturing method in a semiconductor integrated circuit.
2. Description of the Related Art
In recent years, progress in a semiconductor manufacturing technique has been very remarkable, and a semiconductor whose size is 70 nm of the minimum design rule has been mass-produced. Such downsizing is achieved by remarkable progress in downsizing pattern forming techniques such as a mask process technique, an optical lithography technique, and an etching technique. In the generation when a pattern size is sufficiently large, a planar shape of an integrated circuit pattern to be formed on a wafer is written as a design pattern without being processed, a mask pattern faithful to the design pattern is produced, the mask pattern is transferred onto a wafer by means of a projection optical system, and an under-resist layer is etched, whereby a pattern as desired is successfully formed on the wafer. However, as downsizing of an integrated circuit pattern advances, it becomes difficult to faithfully form a pattern in each process, and there occurs a problem that the finally finished dimension of the pattern is deviated from that of the design pattern.
In particular, in a lithography process and an etching process that are the most important to achieve a fine processing, other pattern layouts arranged at the periphery of the pattern to be formed have great effect on dimensional precision of the pattern.
So-called optical proximity correction (OPC) and process proximity correction (PPC) techniques have been developed in order to avoid the above disadvantage. In these correction techniques, an auxiliary pattern is added to the design pattern in advance or the width of the design pattern is increased or decreased in advance so that dimension of a pattern after processed becomes the dimension of the design pattern (a desired value). These techniques have been reported by, for example, Jpn. Pat. Appln. KOKAI Publication No. 09-319067 and SPIE Vol. 2322 (1994) 374 (Large Area Optical Proximity Correction Using Pattern Based Correction, D. M. Newmark, et. al).
It becomes possible to form an integrated circuit pattern written by a designer on a wafer by using the technique. In a currently widely used CPC/PPC techniques, however, it is premised that a process condition is an optimal condition and that a pattern formed on a wafer after corrected is a pattern as written by the designer. In other words, in this technique, a pattern is formed on a wafer as written by the designer, under an optimal condition. Variations in the processes are out of consideration.
Since, in the above technique, so-called process variations (such as focus variation of an exposure device or exposure dose variation) are not considered, there may occur a case in which an integrated circuit pattern formed on a wafer largely changes from a desired shape when such process variations occur. In addition, all of the portions of the integrated circuit pattern, for example, a transistor portion, a wiring portion, and a bend portion of a wiring, are corrected in accordance with the same standard. Therefore, a portion at which the tolerance is large in terms of circuit performance or manufacture is strictly corrected in the same manner as a portion to be strictly managed. This causes an increase in processing time or a complicated mask shape.